Among conventional semiconductor memory devices, a nonvolatile semiconductor memory device having a cell transistor shown in FIG. 5 is known as a nonvolatile semiconductor memory device storing multiple bits of information per cell (Related Art 1). The nonvolatile semiconductor memory device relating to Related Art 1 comprises two band (or strap)-shaped opposite conductivity type regions 123a and 123b formed on the surface of a semiconductor substrate 121 with a band-shaped semiconductor layer 124a of one conductivity type interposed between them, a first floating gate 127a formed on one of the opposite conductivity type regions 123a and a side surface of the semiconductor layer 124a via an insulating film 122a, a second floating gate 127b formed on the other opposite conductivity type region 123b and the other side surface of the semiconductor layer 124a via an insulating film 122b, and a control gate 130a formed on the upper surface of the semiconductor layer 124a via an insulating film 128 (refer to Patent Document 1). The nonvolatile semiconductor memory device relating to Related Art 1 has a highly reliable structure, maintains the localization of the trapped charges even when excessive write operations are performed, and is able to control the dispersion of the threshold voltage. Furthermore, since the floating gates 127a and 127b and the opposite conductivity regions 123a and 123b overlap, it can be miniaturized to such an extent.
A nonvolatile semiconductor memory device shown in FIGS. 6 and 7 is also known as a conventional semiconductor memory device (Related Art 2). The nonvolatile semiconductor memory device relating to Related Art 2 comprises a first diffusion region 207a and a second diffusion region 207b extending in parallel to one another and apart from one another in a memory cell area on the surface of a substrate 201, a selection gate 203a disposed in a region between the first diffusion region 207a and the second diffusion region 207b on the substrate 201 through an insulating film 202, a third diffusion region (221 in FIG. 6) extending in the direction orthogonal to the direction of the selection gate 203a and provided on the surface of the substrate 201 below the selection gate 203a outside the cell region, floating gates 206a disposed in a first region between the first diffusion region 207a and the selection gate 203a and in a second region between the second diffusion region 207b and the selection gate 203a via (interposed with) the insulating film 202, and a plurality of control gates 211 each disposed over the floating gates 206a and the selection gate 203a via an insulating film 208. The first diffusion region 207a, the floating gate 206a, the control gate 211, and the selection gate 203a make up a first unit cell; whereas the second diffusion region 207b, the floating gate 206a, the control gate 211, and the selection gate 203a make up a second unit cell. An inversion layer 220 is created on the surface of the substrate 201 below the selection gate 203a within the cell region by applying a positive voltage to the selection gate 203a (refer to Patent Document 2). The nonvolatile semiconductor memory device relating to Related Art 2 is different from the nonvolatile semiconductor memory device relating to Related Art 1 in the following points: (1) it has the selection gate 203; (2) the inversion layer 220 is formed below the selection gate 203a in the cell region when a positive voltage is applied to the selection gate 203a; (3) the space below each of the floating gates 206a is utilized as a channel; (4) the inversion layers 220 and the third diffusion regions (221 in FIG. 6) are used as current supplying paths on the drain side during read operations.
Compared to the nonvolatile semiconductor memory device relating to Related Art 1, the channel below the selection gate 203a is positioned at a drain side when reading is performed in the nonvolatile semiconductor memory device relating to Related Art 2. Thus, reading from a target storage node of an independent unit cell disposed opposite to a nontarget storage node with the selection gate 203a interposed between them is performed without recourse to the nontarget storage node of the other unit cell. This semiconductor memory device substantially functions as a one-bit cell, therefore, it is advantageous for obtaining stable circuit operation.
A method for manufacturing the nonvolatile semiconductor memory device relating to Related Art 2 will be described with reference to the drawings. FIGS. 8A to 11L illustrate cross sectional views schematically showing the steps of the method for manufacturing the nonvolatile semiconductor memory device relating to Related Art 2.
First, after an element isolation region (not shown in the drawings) is formed on the substrate 201, a well (not shown in the drawings) is created in the cell region on the substrate 201. Then, the third diffusion region (221 in FIG. 6) is formed and the insulating film 202 (for instance a silicon oxide film) is formed on the substrate 201. A selection gate film 203 (for instance a polysilicon film) is formed over the insulating film 202, and an insulating film 210 (for instance a silicon oxide film) is formed over the selection gate film 203. An insulating film 204 (for instance a silicon nitride film) is formed over the insulating film 210, an insulating film 212 (for instance a silicon oxide film) is formed over the insulating film 204, and an insulating film 213 (for instance a silicon nitride film) is formed over the insulating film 212 (step A1; refer to FIG. 8A). Next, a photoresist (not shown in the drawings) is formed over the insulating film 213 for forming the selection gate 203a. The selection gate 203a is formed by selectively etching the insulating film 213, the insulating film 212, the insulating film 204, the insulating film 210, the selection gate (203 in FIG. 8A), and the insulating film 202 using this photoresist as a mask, and then the photoresist is removed (step A2; refer to FIG. 8B). Next, an insulating film 205 (for instance a silicon oxide film) is formed over the entire surface of the substrate (step A3; refer to FIG. 8C).
Next, a floating gate film 206 (for instance a polysilicon film) is deposited over the entire surface of the substrate (step A4; refer to FIG. 9D). Then the floating gate film 206a in the form of side wall is formed on side wall surfaces of the insulating film 202, the selection gate 203a, the insulating film 204, the insulating film 212, and the insulating film 213 by etching back the floating gate film (206 in FIG. 9D) (step A5; refer to FIG. 9E). Next, the first diffusion region 207a and the second diffusion region 207b are formed by ion implantation in the self alignment manner, using the insulating film 205 and the floating gate 206a as a mask (step A6; refer to FIG. 9F).
Next, an insulating film 209 (for instance a CVD silicon oxide film) is deposited over the entire surface of the substrate (step A7; refer to FIG. 10G). Then the insulating film 209 is leveled (flattened) by the CMP method using the insulating film 213 as a stopper (the insulating film 205 over the insulating 213 is removed) (step A8; refer to FIG. 10H). Next, the insulating film 209 is partially and selectively removed (step A9; refer to FIG. 10I).
Then the insulating film (213 in FIG. 10F) is selectively removed (step A10; refer to FIG. 11J). Next, the insulating film 212 (including parts of the insulating film 205 and the insulating film 209) is selectively removed (step A11; refer to FIG. 11K). Note that parts of the insulating film 209 and the insulating film 205 are removed when the insulating film 212 is removed. Then the insulating film 208 (for instance an ONO film) is formed over the entire surface of the substrate (step A12; refer to FIG. 11L).
Then a control gate film (for instance a polysilicon film) is deposited over the entire surface of the substrate, a photoresist (not shown in the drawings) for forming a word line is formed, the band-shaped control gates 211 and the insular floating gates 206a are formed by selectively removing the control gate film, the insulating film 208, and the floating gate 206a using this photoresist as a mask, and then the photoresist is removed (step A13; refer to FIG. 7). Thus the semiconductor memory device having a memory cell is completed.
The read operation of the nonvolatile semiconductor memory device relating to Related Art 2 will be described with reference to the drawings. FIG. 12 is a schematic diagram for explaining the read operation of the semiconductor memory device relating to Related Art 2 (the read operation in a state where electrons are not accumulated in the floating gate).
Referring to FIG. 12, during the read operation in the state where electrons are not accumulated in the floating gate 206a (erase state; low threshold voltage, ON cell), electrons e run from the second diffusion region 207b through the channel below the floating gate 206a when a positive voltage is applied to the control gate 211, the selection gate 203a, and the third diffusion region (221 in FIG. 6). The electrons e further run through the inversion layer 220 formed below the selection gate 203a and move to the third diffusion region (221 in FIG. 6). On the other hand, in a state where electrons are accumulated in the floating gate 206a (a write state; high threshold voltage, OFF cell), the electrons e do not flow when a positive voltage is applied to the control gate 211, the selection gate 203a, and the third diffusion region (221 in FIG. 6) because there is no channel below the floating gate 206a (not shown in the drawing). The read operation is performed by judging data (0/1) according to whether or not the electrons e flow.
[Patent Document 1]
Japanese Patent No. 3249811
[Patent Document 2]
U.S. Patent Publication No. US2005-0029577A1
[Patent Document 3]
Japanese Patent Kokai Publication No. JP-A-11-354742
The entire disclosures of the documents mentioned above are incorporated herein with reference thereto.